From db3118b916b1a0b61e4524e5e214bf96b7018f81 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 3 Apr 2017 00:18:07 +0800
Subject: [PATCH] drtio: use BlindTransfer for error reporting

---
 artiq/gateware/drtio/rt_errors_satellite.py | 11 ++++++-----
 artiq/gateware/drtio/rt_packet_master.py    |  6 +++---
 artiq/gateware/rtio/cdc.py                  |  9 +++++----
 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/artiq/gateware/drtio/rt_errors_satellite.py b/artiq/gateware/drtio/rt_errors_satellite.py
index cf9af97cf..3a67e88d8 100644
--- a/artiq/gateware/drtio/rt_errors_satellite.py
+++ b/artiq/gateware/drtio/rt_errors_satellite.py
@@ -1,9 +1,10 @@
 """Protocol error reporting for satellites."""
 
 from migen import *
-from migen.genlib.cdc import PulseSynchronizer
 from misoc.interconnect.csr import *
 
+from artiq.gateware.rtio.cdc import BlindTransfer
+
 
 class RTErrorsSatellite(Module, AutoCSR):
     def __init__(self, rt_packet, ios):
@@ -13,12 +14,12 @@ class RTErrorsSatellite(Module, AutoCSR):
         def error_csr(csr, *sources):
             for n, source in enumerate(sources):
                 pending = Signal(related=source)
-                ps = PulseSynchronizer("rtio", "sys")
-                self.submodules += ps
-                self.comb += ps.i.eq(source)
+                xfer = BlindTransfer(odomain="sys")
+                self.submodules += xfer
+                self.comb += xfer.i.eq(source)
                 self.sync += [
                     If(csr.re & csr.r[n], pending.eq(0)),
-                    If(ps.o, pending.eq(1))
+                    If(xfer.o, pending.eq(1))
                 ]
                 self.comb += csr.w[n].eq(pending)
 
diff --git a/artiq/gateware/drtio/rt_packet_master.py b/artiq/gateware/drtio/rt_packet_master.py
index bec036161..a32004ebd 100644
--- a/artiq/gateware/drtio/rt_packet_master.py
+++ b/artiq/gateware/drtio/rt_packet_master.py
@@ -5,7 +5,7 @@ from migen.genlib.fsm import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.cdc import PulseSynchronizer
 
-from artiq.gateware.rtio.cdc import GrayCodeTransfer
+from artiq.gateware.rtio.cdc import GrayCodeTransfer, BlindTransfer
 from artiq.gateware.drtio.rt_serializer import *
 
 
@@ -252,8 +252,8 @@ class RTPacketMaster(Module):
             read_timestamp.eq(rx_dp.packet_as["read_reply"].timestamp)
         ]
 
-        err_unknown_packet_type = PulseSynchronizer("rtio_rx", "sys")
-        err_packet_truncated = PulseSynchronizer("rtio_rx", "sys")
+        err_unknown_packet_type = BlindTransfer("rtio_rx", "sys")
+        err_packet_truncated = BlindTransfer("rtio_rx", "sys")
         self.submodules += err_unknown_packet_type, err_packet_truncated
         self.comb += [
             self.err_unknown_packet_type.eq(err_unknown_packet_type.o),
diff --git a/artiq/gateware/rtio/cdc.py b/artiq/gateware/rtio/cdc.py
index bc561ebbf..af93b4105 100644
--- a/artiq/gateware/rtio/cdc.py
+++ b/artiq/gateware/rtio/cdc.py
@@ -47,15 +47,16 @@ class RTIOCounter(Module):
 
 
 class BlindTransfer(Module):
-    def __init__(self):
+    def __init__(self, idomain="rio", odomain="rsys"):
         self.i = Signal()
         self.o = Signal()
 
-        ps = PulseSynchronizer("rio", "rsys")
-        ps_ack = PulseSynchronizer("rsys", "rio")
+        ps = PulseSynchronizer(idomain, odomain)
+        ps_ack = PulseSynchronizer(odomain, idomain)
         self.submodules += ps, ps_ack
         blind = Signal()
-        self.sync.rio += [
+        isync = getattr(self.sync, idomain)
+        isync += [
             If(self.i, blind.eq(1)),
             If(ps_ack.o, blind.eq(0))
         ]