M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 11:48:27 +08:00
Code Issues Projects Releases Wiki Activity

remove dead commented code

Browse Source
This commit is contained in:
occheung 2024-09-03 11:55:34 +08:00
parent 2c0a4c0bae
commit d935c22aad
1 changed files with 0 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
artiq/firmware/libboard_misoc/spiflash.rs
View File

@ -114,40 +114,6 @@ pub unsafe fn write(mut addr: usize, mut data: &[u8]) {
}
}
// pub unsafe fn write_image(image: &[u8]) {
// let image = &image[..];
// let actual_crc = crc32::checksum_ieee(image);
// if actual_crc == expected_crc {
// let mut reader = Cursor::new(header);
// let bin_no = reader.read_u32().unwrap() as usize;
// for _ in 0..bin_no {
// let bin_name = reader.read_string().unwrap();
// let offset = reader.read_u32().unwrap() as usize;
// let len = reader.read_u32().unwrap() as usize;
// let origin = match bin_name.as_str() {
// "gateware" => 0,
// "bootloader" => mem::ROM_BASE,
// "firmware" => mem::FLASH_BOOT_ADDRESS,
// _ => {
// error!("unexpected binary component {}", bin_name);
// return Ok(Reply::Error.write_to(stream)?);
// }
// };
// unsafe {
// spiflash::flash_binary(origin, &image[offset..offset+len]);
// }
// }
// reboot(_io, stream)?;
// } else {
// error!("CRC failed in SDRAM (actual {:08x}, expected {:08x})", actual_crc, expected_crc);
// Reply::Error.write_to(stream)?;
// }
// }
pub unsafe fn flash_binary(origin: usize, payload: &[u8]) {
assert!((origin & (SECTOR_SIZE - 1)) == 0);
let mut offset = 0;