mirror of https://github.com/m-labs/artiq.git
gtp_7series: flexible QPLL channel selection
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parent
9f87c34a94
commit
d6157514c7
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@ -43,8 +43,7 @@ class GTPSingle(Module):
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txdata = Signal(20)
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txdata = Signal(20)
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rxdata = Signal(20)
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rxdata = Signal(20)
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rxphaligndone = Signal()
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rxphaligndone = Signal()
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self.specials += \
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gtp_params = dict(
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Instance("GTPE2_CHANNEL",
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# Reset modes
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# Reset modes
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i_GTRESETSEL=0,
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i_GTRESETSEL=0,
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i_RESETOVRD=0,
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i_RESETOVRD=0,
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@ -77,16 +76,11 @@ class GTPSingle(Module):
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_TO_P2=0x64,
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p_PD_TRANS_TIME_TO_P2=0x64,
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# QPLL - must use channel 1!
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i_PLL1CLK=qpll_channel.clk,
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i_PLL1REFCLK=qpll_channel.refclk,
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# TX clock
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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o_TXOUTCLK=self.txoutclk,
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p_TXOUT_DIV=2,
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p_TXOUT_DIV=2,
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i_TXSYSCLKSEL=0b11,
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i_TXOUTCLKSEL=0b11,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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# TX Startup/Reset
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@ -136,7 +130,6 @@ class GTPSingle(Module):
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p_TX_CLK25_DIV=5,
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p_TX_CLK25_DIV=5,
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p_RX_XCLK_SEL="RXUSR",
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p_RX_XCLK_SEL="RXUSR",
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p_RXOUT_DIV=2,
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p_RXOUT_DIV=2,
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i_RXSYSCLKSEL=0b11,
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i_RXOUTCLKSEL=0b010,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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@ -168,6 +161,27 @@ class GTPSingle(Module):
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o_GTPTXP=pads.txp,
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o_GTPTXP=pads.txp,
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o_GTPTXN=pads.txn
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o_GTPTXN=pads.txn
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)
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)
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if qpll_channel.index == 0:
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gtp_params.update(
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i_RXSYSCLKSEL=0b00,
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i_TXSYSCLKSEL=0b00,
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i_PLL0CLK=qpll_channel.clk,
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i_PLL0REFCLK=qpll_channel.refclk,
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i_PLL1CLK=0,
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i_PLL1REFCLK=0,
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)
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elif qpll_channel.index == 1:
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gtp_params.update(
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i_RXSYSCLKSEL=0b11,
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i_TXSYSCLKSEL=0b11,
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i_PLL0CLK=0,
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i_PLL0REFCLK=0,
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i_PLL1CLK=qpll_channel.clk,
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i_PLL1REFCLK=qpll_channel.refclk,
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)
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else:
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raise ValueError
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self.specials += Instance("GTPE2_CHANNEL", **gtp_params)
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# tx clocking
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# tx clocking
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tx_reset_deglitched = Signal()
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tx_reset_deglitched = Signal()
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