mirror of https://github.com/m-labs/artiq.git
jesd204sync: reset and check lock status of DDMTD helper PLL in firmware
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@ -28,6 +28,20 @@ const DDMTD_DITHER_BITS: i32 = 1;
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const DDMTD_N_SHIFT: i32 = RAW_DDMTD_N_SHIFT + DDMTD_DITHER_BITS;
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const DDMTD_N_SHIFT: i32 = RAW_DDMTD_N_SHIFT + DDMTD_DITHER_BITS;
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const DDMTD_N: i32 = 1 << DDMTD_N_SHIFT;
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const DDMTD_N: i32 = 1 << DDMTD_N_SHIFT;
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fn init_ddmtd() -> Result<(), &'static str> {
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unsafe {
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csr::sysref_ddmtd::reset_write(1);
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clock::spin_us(1);
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csr::sysref_ddmtd::reset_write(0);
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clock::spin_us(100);
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if csr::sysref_ddmtd::locked_read() != 0 {
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Ok(())
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} else {
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Err("DDMTD helper PLL failed to lock")
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}
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}
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}
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fn measure_ddmdt_phase_raw() -> i32 {
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fn measure_ddmdt_phase_raw() -> i32 {
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unsafe { csr::sysref_ddmtd::dt_read() as i32 }
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unsafe { csr::sysref_ddmtd::dt_read() as i32 }
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}
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}
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@ -276,6 +290,7 @@ pub fn sysref_rtio_align() -> Result<(), &'static str> {
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}
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}
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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init_ddmtd()?;
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test_ddmtd_stability(true, 4)?;
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test_ddmtd_stability(true, 4)?;
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test_ddmtd_stability(false, 1)?;
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test_ddmtd_stability(false, 1)?;
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test_slip_ddmtd()?;
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test_slip_ddmtd()?;
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@ -95,11 +95,14 @@ class DDMTDEdgeDetector(Module):
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class DDMTD(Module, AutoCSR):
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class DDMTD(Module, AutoCSR):
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def __init__(self, input_pads, rtio_clk_freq=150e6):
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def __init__(self, input_pads, rtio_clk_freq=150e6):
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N = 64
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N = 64
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self.reset = CSRStorage(reset=1)
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self.locked = CSRStatus()
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self.dt = CSRStatus(N.bit_length())
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self.dt = CSRStatus(N.bit_length())
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# # #
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# # #
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self.clock_domains.cd_helper = ClockDomain(reset_less=True)
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self.clock_domains.cd_helper = ClockDomain(reset_less=True)
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helper_locked = Signal()
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helper_fb = Signal()
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helper_fb = Signal()
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helper_output = Signal()
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helper_output = Signal()
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@ -110,7 +113,8 @@ class DDMTD(Module, AutoCSR):
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Instance("MMCME2_BASE",
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=ResetSignal("rtio"),
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i_RST=self.reset.storage,
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o_LOCKED=helper_locked,
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# VCO at 1200MHz with 150MHz RTIO frequency
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# VCO at 1200MHz with 150MHz RTIO frequency
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p_CLKFBOUT_MULT_F=8.0,
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p_CLKFBOUT_MULT_F=8.0,
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@ -122,6 +126,7 @@ class DDMTD(Module, AutoCSR):
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p_CLKOUT0_DIVIDE_F=8.125,
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p_CLKOUT0_DIVIDE_F=8.125,
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o_CLKOUT0=helper_output,
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o_CLKOUT0=helper_output,
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),
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),
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MultiReg(helper_locked, self.locked.status),
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Instance("BUFG", i_I=helper_output, o_O=self.cd_helper.clk),
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Instance("BUFG", i_I=helper_output, o_O=self.cd_helper.clk),
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Instance("IBUFDS", i_I=input_pads.p, i_IB=input_pads.n, o_O=input_se),
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Instance("IBUFDS", i_I=input_pads.p, i_IB=input_pads.n, o_O=input_se),
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Instance("FD", i_C=self.cd_helper.clk, i_D=input_se, o_Q=beat1, attr={("IOB", "TRUE")}),
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Instance("FD", i_C=self.cd_helper.clk, i_D=input_se, o_Q=beat1, attr={("IOB", "TRUE")}),
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