From d3c608aaec80dad003bb3279d288bb4afc9755a0 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 31 Jan 2019 15:11:16 +0800 Subject: [PATCH] jesd204sync: reset and check lock status of DDMTD helper PLL in firmware --- artiq/firmware/libboard_artiq/jesd204sync.rs | 15 +++++++++++++++ artiq/gateware/jesd204_tools.py | 7 ++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/artiq/firmware/libboard_artiq/jesd204sync.rs b/artiq/firmware/libboard_artiq/jesd204sync.rs index 1804e8cbe..29f533a5a 100644 --- a/artiq/firmware/libboard_artiq/jesd204sync.rs +++ b/artiq/firmware/libboard_artiq/jesd204sync.rs @@ -28,6 +28,20 @@ const DDMTD_DITHER_BITS: i32 = 1; const DDMTD_N_SHIFT: i32 = RAW_DDMTD_N_SHIFT + DDMTD_DITHER_BITS; const DDMTD_N: i32 = 1 << DDMTD_N_SHIFT; +fn init_ddmtd() -> Result<(), &'static str> { + unsafe { + csr::sysref_ddmtd::reset_write(1); + clock::spin_us(1); + csr::sysref_ddmtd::reset_write(0); + clock::spin_us(100); + if csr::sysref_ddmtd::locked_read() != 0 { + Ok(()) + } else { + Err("DDMTD helper PLL failed to lock") + } + } +} + fn measure_ddmdt_phase_raw() -> i32 { unsafe { csr::sysref_ddmtd::dt_read() as i32 } } @@ -276,6 +290,7 @@ pub fn sysref_rtio_align() -> Result<(), &'static str> { } pub fn sysref_auto_rtio_align() -> Result<(), &'static str> { + init_ddmtd()?; test_ddmtd_stability(true, 4)?; test_ddmtd_stability(false, 1)?; test_slip_ddmtd()?; diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index 1806b90ca..a5151acf3 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -95,11 +95,14 @@ class DDMTDEdgeDetector(Module): class DDMTD(Module, AutoCSR): def __init__(self, input_pads, rtio_clk_freq=150e6): N = 64 + self.reset = CSRStorage(reset=1) + self.locked = CSRStatus() self.dt = CSRStatus(N.bit_length()) # # # self.clock_domains.cd_helper = ClockDomain(reset_less=True) + helper_locked = Signal() helper_fb = Signal() helper_output = Signal() @@ -110,7 +113,8 @@ class DDMTD(Module, AutoCSR): Instance("MMCME2_BASE", p_CLKIN1_PERIOD=1e9/rtio_clk_freq, i_CLKIN1=ClockSignal("rtio"), - i_RST=ResetSignal("rtio"), + i_RST=self.reset.storage, + o_LOCKED=helper_locked, # VCO at 1200MHz with 150MHz RTIO frequency p_CLKFBOUT_MULT_F=8.0, @@ -122,6 +126,7 @@ class DDMTD(Module, AutoCSR): p_CLKOUT0_DIVIDE_F=8.125, o_CLKOUT0=helper_output, ), + MultiReg(helper_locked, self.locked.status), Instance("BUFG", i_I=helper_output, o_O=self.cd_helper.clk), Instance("IBUFDS", i_I=input_pads.p, i_IB=input_pads.n, o_O=input_se), Instance("FD", i_C=self.cd_helper.clk, i_D=input_se, o_Q=beat1, attr={("IOB", "TRUE")}),