M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

examples: fix RTIO clocks to 125 MHz

This commit is contained in:
Harry Ho 2021-12-13 10:41:48 +08:00
parent 77c4d2f013
commit d3869c966e
4 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/examples/kasli_drtioswitching/device_db.py
View File

@ -5,7 +5,7 @@ device_db = {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
"arguments": {"host": core_addr, "ref_period": 1/(8*125e6)}
},
"core_log": {
"type": "controller",

4
artiq/examples/kasli_sawgmaster/device_db.py
View File

@ -5,7 +5,7 @@ device_db = {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
"arguments": {"host": core_addr, "ref_period": 1/(8*125e6)}
},
"core_log": {
"type": "controller",
@ -69,7 +69,7 @@ device_db.update(
"arguments": {
"spi_device": "spi_urukul0",
"io_update_device": "ttl_urukul0_io_update",
"refclk": 150e6,
"refclk": 125e6,
"clk_sel": 2
}
}

2
artiq/examples/metlino_sayma_ttl/device_db.py
View File

@ -5,7 +5,7 @@ device_db = {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
"arguments": {"host": core_addr, "ref_period": 1/(8*125e6)}
},
"core_log": {
"type": "controller",

2
artiq/examples/sayma_master/device_db.py
View File

@ -5,7 +5,7 @@ device_db = {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
"arguments": {"host": core_addr, "ref_period": 1/(8*125e6)}
},
"core_log": {
"type": "controller",