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siphaser: remove support for 150 MHz RTIO clock 

* Sayma AMC no longer uses 150 MHz RTIO clock after 1 GS/s upgrade.
This commit is contained in:
Harry Ho 2021-12-13 10:37:50 +08:00
parent 23f5796d67
commit 77c4d2f013
1 changed files with 6 additions and 6 deletions
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12
artiq/gateware/drtio/siphaser.py
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@ -4,20 +4,20 @@ from migen.genlib.cdc import MultiReg, PulseSynchronizer
from misoc.interconnect.csr import *
# This code assumes 125/62.5MHz reference clock and 125MHz or 150MHz RTIO
# This code assumes 125/62.5MHz reference clock and 125MHz RTIO
# frequency.
class SiPhaser7Series(Module, AutoCSR):
def __init__(self, si5324_clkin, rx_synchronizer,
ref_clk=None, ref_div2=False, ultrascale=False, rtio_clk_freq=150e6):
ref_clk=None, ref_div2=False, ultrascale=False, rtio_clk_freq=125e6):
self.switch_clocks = CSRStorage()
self.phase_shift = CSR()
self.phase_shift_done = CSRStatus(reset=1)
self.error = CSR()
assert rtio_clk_freq in (125e6, 150e6)
assert rtio_clk_freq == 125e6
# 125MHz/62.5MHz reference clock to 125MHz/150MHz. VCO @ 750MHz.
# 125MHz reference clock to 125MHz. VCO @ 750MHz.
# Used to provide a startup clock to the transceiver through the Si,
# we do not use the crystal reference so that the PFD (f3) frequency
# can be high.
@ -43,8 +43,8 @@ class SiPhaser7Series(Module, AutoCSR):
else:
mmcm_freerun_output = mmcm_freerun_output_raw
# 125MHz/150MHz to 125MHz/150MHz with controllable phase shift,
# VCO @ 1000MHz/1200MHz.
# 125MHz to 125MHz with controllable phase shift,
# VCO @ 1000MHz.
# Inserted between CDR and output to Si, used to correct
# non-determinstic skew of Si5324.
mmcm_ps_fb = Signal()