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phaser: fix frequency comment

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This commit is contained in:
Robert Jördens 2016-11-05 16:54:23 +01:00
parent b14fcd41e4
commit d158c69be0
1 changed files with 1 additions and 1 deletions
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artiq/gateware/targets/kc705.py
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@ -415,7 +415,7 @@ class _PhaserCRG(Module, AutoCSR):
# Warning: CLKINSEL=0 means CLKIN2 is selected # Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage, i_CLKINSEL=~self._clock_sel.storage,
# VCO @ 1GHz when using 125MHz input # VCO @ 1GHz when using 250MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=2, p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=2,
i_CLKFBIN=self.cd_rtio.clk, i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage, i_RST=self._pll_reset.storage,