From d158c69be0ec23910d98ffc11a4065d3fca0634b Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Sat, 5 Nov 2016 16:54:23 +0100
Subject: [PATCH] phaser: fix frequency comment

---
 artiq/gateware/targets/kc705.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 57a31da9c..0e1e33c16 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -415,7 +415,7 @@ class _PhaserCRG(Module, AutoCSR):
                      # Warning: CLKINSEL=0 means CLKIN2 is selected
                      i_CLKINSEL=~self._clock_sel.storage,
 
-                     # VCO @ 1GHz when using 125MHz input
+                     # VCO @ 1GHz when using 250MHz input
                      p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=2,
                      i_CLKFBIN=self.cd_rtio.clk,
                      i_RST=self._pll_reset.storage,