mirror of https://github.com/m-labs/artiq.git
suservo: set input delays
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@ -603,13 +603,29 @@ class SUServo(_StandaloneBase):
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self.add_rtio(rtio_channels)
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platform.add_period_constraint(self.cd_ret.clk, 8.)
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platform.add_period_constraint(sampler_pads.clkout_p, 8.)
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platform.add_false_path_constraints(
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self.cd_ret.clk,
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sampler_pads.clkout_p,
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self.rtio_crg.cd_rtio.clk)
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platform.add_false_path_constraints(
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self.cd_ret.clk,
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sampler_pads.clkout_p,
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self.crg.cd_sys.clk)
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for i in "abcd":
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port = getattr(sampler_pads, "sdo{}_p".format(i))
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platform.add_platform_command(
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-max 6 [get_ports {port}]\n"
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-min 3.5 [get_ports {port}]\n"
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-max 6 [get_ports {port}] -clock_fall -add_delay\n"
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-min 3.5 [get_ports {port}] -clock_fall -add_delay",
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clk=sampler_pads.clkout_p, port=port)
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class SYSU(_StandaloneBase):
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