From d0258b9b2d60f2f09d6af065240bded3100a39bb Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 24 Apr 2018 14:40:37 +0000 Subject: [PATCH] suservo: set input delays --- artiq/gateware/targets/kasli.py | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index bbad616dd..2619a8656 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -603,13 +603,29 @@ class SUServo(_StandaloneBase): self.add_rtio(rtio_channels) - platform.add_period_constraint(self.cd_ret.clk, 8.) + platform.add_period_constraint(sampler_pads.clkout_p, 8.) platform.add_false_path_constraints( - self.cd_ret.clk, + sampler_pads.clkout_p, self.rtio_crg.cd_rtio.clk) platform.add_false_path_constraints( - self.cd_ret.clk, + sampler_pads.clkout_p, self.crg.cd_sys.clk) + for i in "abcd": + port = getattr(sampler_pads, "sdo{}_p".format(i)) + platform.add_platform_command( + "set_input_delay -clock [get_clocks " + "-include_generated_clocks -of [get_nets {clk}]] " + "-max 6 [get_ports {port}]\n" + "set_input_delay -clock [get_clocks " + "-include_generated_clocks -of [get_nets {clk}]] " + "-min 3.5 [get_ports {port}]\n" + "set_input_delay -clock [get_clocks " + "-include_generated_clocks -of [get_nets {clk}]] " + "-max 6 [get_ports {port}] -clock_fall -add_delay\n" + "set_input_delay -clock [get_clocks " + "-include_generated_clocks -of [get_nets {clk}]] " + "-min 3.5 [get_ports {port}] -clock_fall -add_delay", + clk=sampler_pads.clkout_p, port=port) class SYSU(_StandaloneBase):