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suservo: set input delays

This commit is contained in:
Robert Jördens 2018-04-24 14:40:37 +00:00
parent fe75064c1e
commit d0258b9b2d
1 changed files with 19 additions and 3 deletions
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22
artiq/gateware/targets/kasli.py
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@ -603,13 +603,29 @@ class SUServo(_StandaloneBase):
self.add_rtio(rtio_channels) self.add_rtio(rtio_channels)
platform.add_period_constraint(self.cd_ret.clk, 8.) platform.add_period_constraint(sampler_pads.clkout_p, 8.)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.cd_ret.clk, sampler_pads.clkout_p,
self.rtio_crg.cd_rtio.clk) self.rtio_crg.cd_rtio.clk)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.cd_ret.clk, sampler_pads.clkout_p,
self.crg.cd_sys.clk) self.crg.cd_sys.clk)
for i in "abcd":
port = getattr(sampler_pads, "sdo{}_p".format(i))
platform.add_platform_command(
"set_input_delay -clock [get_clocks "
"-include_generated_clocks -of [get_nets {clk}]] "
"-max 6 [get_ports {port}]\n"
"set_input_delay -clock [get_clocks "
"-include_generated_clocks -of [get_nets {clk}]] "
"-min 3.5 [get_ports {port}]\n"
"set_input_delay -clock [get_clocks "
"-include_generated_clocks -of [get_nets {clk}]] "
"-max 6 [get_ports {port}] -clock_fall -add_delay\n"
"set_input_delay -clock [get_clocks "
"-include_generated_clocks -of [get_nets {clk}]] "
"-min 3.5 [get_ports {port}] -clock_fall -add_delay",
clk=sampler_pads.clkout_p, port=port)
class SYSU(_StandaloneBase): class SYSU(_StandaloneBase):