mirror of https://github.com/m-labs/artiq.git
gateware/kc705: add I2C GPIO core for QC2
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@ -291,8 +291,17 @@ class NIST_CLOCK(_NIST_Ions):
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class NIST_QC2(_NIST_Ions):
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class NIST_QC2(_NIST_Ions):
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"""
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 12 DDS channels. Current implementation for single backplane.
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and 12 DDS channels. Current implementation for single backplane.
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"""
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"""
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csr_map = {
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"i2c": None
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}
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csr_map.update(_NIST_Ions.csr_map)
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mem_map = {
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"i2c": 0x30000000 # (shadow @0xb0000000)
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}
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mem_map.update(_NIST_Ions.mem_map)
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def __init__(self, cpu_type="or1k", **kwargs):
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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@ -341,6 +350,10 @@ class NIST_QC2(_NIST_Ions):
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assert self.rtio.fine_ts_width <= 3
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assert self.rtio.fine_ts_width <= 3
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self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width
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self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width
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i2c = platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.register_kernel_cpu_csrdevice("i2c")
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def main():
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def main():
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parser = argparse.ArgumentParser(
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parser = argparse.ArgumentParser(
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