From cfe72c72a24173ef96ff48a76f12d2a087c61c96 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 3 Mar 2016 15:32:10 +0800 Subject: [PATCH] gateware/kc705: add I2C GPIO core for QC2 --- artiq/gateware/targets/kc705.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index e7268d3d0..3215c7ec0 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -291,8 +291,17 @@ class NIST_CLOCK(_NIST_Ions): class NIST_QC2(_NIST_Ions): """ NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane - and 12 DDS channels. Current implementation for single backplane. + and 12 DDS channels. Current implementation for single backplane. """ + csr_map = { + "i2c": None + } + csr_map.update(_NIST_Ions.csr_map) + mem_map = { + "i2c": 0x30000000 # (shadow @0xb0000000) + } + mem_map.update(_NIST_Ions.mem_map) + def __init__(self, cpu_type="or1k", **kwargs): _NIST_Ions.__init__(self, cpu_type, **kwargs) @@ -341,6 +350,10 @@ class NIST_QC2(_NIST_Ions): assert self.rtio.fine_ts_width <= 3 self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width + i2c = platform.request("i2c") + self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) + self.register_kernel_cpu_csrdevice("i2c") + def main(): parser = argparse.ArgumentParser(