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test_full_stack: restore missing check_ttls

This commit is contained in:
mwojcik 2023-01-10 17:09:27 +08:00 committed by Sébastien Bourdeauducq
parent 627504b60e
commit cd860beda2
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/test/drtio/test_full_stack.py
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@ -169,7 +169,7 @@ class TestFullStack(unittest.TestCase):
yield from tb.sync() yield from tb.sync()
run_simulation(tb.dut, run_simulation(tb.dut,
{"sys": test()}, self.clocks) {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks)
self.assertEqual(ttl_changes, correct_ttl_changes) self.assertEqual(ttl_changes, correct_ttl_changes)
def test_underflow(self): def test_underflow(self):
@ -214,7 +214,7 @@ class TestFullStack(unittest.TestCase):
yield from tb.sync() yield from tb.sync()
run_simulation(tb.dut, run_simulation(tb.dut,
{"sys": test()}, self.clocks) {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks)
self.assertEqual(ttl_changes, correct_ttl_changes) self.assertEqual(ttl_changes, correct_ttl_changes)
def test_write_underflow(self): def test_write_underflow(self):
@ -284,7 +284,7 @@ class TestFullStack(unittest.TestCase):
yield dut.phy2.rtlink.i.stb.eq(0) yield dut.phy2.rtlink.i.stb.eq(0)
run_simulation(dut, run_simulation(dut,
{"sys": test()}, self.clocks) {"sys": [test(), generate_input()]}, self.clocks)
def test_echo(self): def test_echo(self):
dut = DUT(2) dut = DUT(2)