From cd860beda24eac6da418254cdc61db9d83945bae Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 10 Jan 2023 17:09:27 +0800 Subject: [PATCH] test_full_stack: restore missing check_ttls --- artiq/gateware/test/drtio/test_full_stack.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index 4c7d367b2..61fb43d2a 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -169,7 +169,7 @@ class TestFullStack(unittest.TestCase): yield from tb.sync() run_simulation(tb.dut, - {"sys": test()}, self.clocks) + {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks) self.assertEqual(ttl_changes, correct_ttl_changes) def test_underflow(self): @@ -214,7 +214,7 @@ class TestFullStack(unittest.TestCase): yield from tb.sync() run_simulation(tb.dut, - {"sys": test()}, self.clocks) + {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks) self.assertEqual(ttl_changes, correct_ttl_changes) def test_write_underflow(self): @@ -284,7 +284,7 @@ class TestFullStack(unittest.TestCase): yield dut.phy2.rtlink.i.stb.eq(0) run_simulation(dut, - {"sys": test()}, self.clocks) + {"sys": [test(), generate_input()]}, self.clocks) def test_echo(self): dut = DUT(2)