diff --git a/artiq/gateware/dsp/sawg.py b/artiq/gateware/dsp/sawg.py
index 5b432cd54..177a6e8df 100644
--- a/artiq/gateware/dsp/sawg.py
+++ b/artiq/gateware/dsp/sawg.py
@@ -184,8 +184,10 @@ class Channel(Module, SatAddMixin):
         ]
         self.sync += [
             hbf[0].i.eq(self.sat_add((a1.xo[0], a2.xo[0]),
+                width=len(hbf[0].i),
                 limits=cfg.limits[1], clipped=cfg.clipped[1])),
             hbf[1].i.eq(self.sat_add((a1.yo[0], a2.yo[0]),
+                width=len(hbf[1].i),
                 limits=cfg.limits[1], clipped=cfg.clipped[1])),
         ]
         # wire up outputs and q_{i,o} exchange
@@ -200,6 +202,7 @@ class Channel(Module, SatAddMixin):
             ]
             self.sync += [
                 o.eq(self.sat_add((o_offset, o_x, o_y),
+                    width=len(o),
                     limits=cfg.limits[0], clipped=cfg.clipped[0])),
             ]
 
diff --git a/artiq/gateware/dsp/tools.py b/artiq/gateware/dsp/tools.py
index a9142fa76..c198d1706 100644
--- a/artiq/gateware/dsp/tools.py
+++ b/artiq/gateware/dsp/tools.py
@@ -30,14 +30,15 @@ def eqh(a, b):
 
 class SatAddMixin:
     """Signed saturating addition mixin"""
-    def sat_add(self, a, *, width=None, limits=None, clipped=None):
+    def sat_add(self, a, width, limits=None, clipped=None):
         a = list(a)
         # assert all(value_bits_sign(ai)[1] for ai in a)
-        if width is None:
-            width = max(value_bits_sign(ai)[0] for ai in a)
+        max_width = max(value_bits_sign(ai)[0] for ai in a)
         carry = log2_int(len(a), need_pow2=False)
-        full = Signal((width + carry, True))
+        full = Signal((max_width + carry, True))
         limited = Signal((width, True))
+        carry = len(full) - width
+        assert carry >= 0
         clip = Signal(2)
         sign = Signal()
         if clipped is not None: