mirror of https://github.com/m-labs/artiq.git
gateware/ad9858: use WaitTimer from Migen
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@ -1,25 +1,11 @@
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from migen.fhdl.std import *
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from migen.fhdl.std import *
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from migen.genlib.fsm import *
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from migen.genlib.fsm import *
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from migen.genlib.misc import WaitTimer
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from migen.bus import wishbone
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from migen.sim.generic import run_simulation
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class WaitTimer(Module):
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def __init__(self, t):
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self.wait = Signal()
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self.done = Signal()
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# # #
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count = Signal(bits_for(t), reset=t)
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self.comb += self.done.eq(count == 0)
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self.sync += \
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If(self.wait,
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If(~self.done, count.eq(count - 1))
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).Else(count.eq(count.reset))
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class AD9858(Module):
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class AD9858(Module):
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"""Wishbone interface to the AD9858 DDS chip.
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"""Wishbone interface to the AD9858 DDS chip.
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