diff --git a/artiq/gateware/ad9858.py b/artiq/gateware/ad9858.py
index 26c790672..d620cac43 100644
--- a/artiq/gateware/ad9858.py
+++ b/artiq/gateware/ad9858.py
@@ -1,25 +1,11 @@
 from migen.fhdl.std import *
 from migen.genlib.fsm import *
+from migen.genlib.misc import WaitTimer
 from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 
-class WaitTimer(Module):
-    def __init__(self, t):
-        self.wait = Signal()
-        self.done = Signal()
-
-        # # #
-
-        count = Signal(bits_for(t), reset=t)
-        self.comb += self.done.eq(count == 0)
-        self.sync += \
-            If(self.wait,
-                If(~self.done, count.eq(count - 1))
-            ).Else(count.eq(count.reset))
-
-
 class AD9858(Module):
     """Wishbone interface to the AD9858 DDS chip.