metlino: fix CSR collisions

Closes #1425
2020-05-29 15:59:44 +08:00 · 2020-05-29 15:59:44 +08:00 · cb76f9da89
parent bd9eec15c0
commit cb76f9da89
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/targets/metlino.py
+++ b/artiq/gateware/targets/metlino.py
@ -46,6 +46,7 @@ class Master(MiniSoC, AMPSoC):
                         integrated_sram_size=8192,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
+                         csr_address_width=15,
                         **kwargs)
        AMPSoC.__init__(self)
        add_identifier(self)