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zotino: default div_read unified with ad53xx at 16, fix ad53xx doc

pull/1740/head
Harry Ho 2021-08-05 16:54:36 +08:00 committed by Sébastien Bourdeauducq
parent 6b88ea563d
commit c9608c0a89
2 changed files with 7 additions and 7 deletions
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6
artiq/coredevice/ad53xx.py
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@ -127,9 +127,9 @@ class AD53xx:
transactions (default: 1) transactions (default: 1)
:param div_write: SPI clock divider for write operations (default: 4, :param div_write: SPI clock divider for write operations (default: 4,
50MHz max SPI clock with {t_high, t_low} >=8ns) 50MHz max SPI clock with {t_high, t_low} >=8ns)
:param div_read: SPI clock divider for read operations (default: 8, not :param div_read: SPI clock divider for read operations (default: 16, not
optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO
valid) valid, and suggests the SPI speed for reads should be <=20 MHz)
:param vref: DAC reference voltage (default: 5.) :param vref: DAC reference voltage (default: 5.)
:param offset_dacs: Initial register value for the two offset DACs, device :param offset_dacs: Initial register value for the two offset DACs, device
dependent and must be set correctly for correct voltage to mu dependent and must be set correctly for correct voltage to mu

8
artiq/coredevice/zotino.py
View File

@ -27,15 +27,15 @@ class Zotino(AD53xx):
:param clr_device: CLR RTIO TTLOut channel name. :param clr_device: CLR RTIO TTLOut channel name.
:param div_write: SPI clock divider for write operations (default: 4, :param div_write: SPI clock divider for write operations (default: 4,
50MHz max SPI clock) 50MHz max SPI clock)
:param div_read: SPI clock divider for read operations (default: 8, not :param div_read: SPI clock divider for read operations (default: 16, not
optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO
valid) valid, and suggests the SPI speed for reads should be <=20 MHz)
:param vref: DAC reference voltage (default: 5.) :param vref: DAC reference voltage (default: 5.)
:param core_device: Core device name (default: "core") :param core_device: Core device name (default: "core")
""" """
def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None, def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
div_write=4, div_read=8, vref=5., core="core"): div_write=4, div_read=16, vref=5., core="core"):
AD53xx.__init__(self, dmgr=dmgr, spi_device=spi_device, AD53xx.__init__(self, dmgr=dmgr, spi_device=spi_device,
ldac_device=ldac_device, clr_device=clr_device, ldac_device=ldac_device, clr_device=clr_device,
chip_select=_SPI_CS_DAC, div_write=div_write, chip_select=_SPI_CS_DAC, div_write=div_write,