From c9608c0a89c146fff66b7918f3e3ed349d52ab5f Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 5 Aug 2021 16:54:36 +0800 Subject: [PATCH] zotino: default div_read unified with ad53xx at 16, fix ad53xx doc --- artiq/coredevice/ad53xx.py | 6 +++--- artiq/coredevice/zotino.py | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/artiq/coredevice/ad53xx.py b/artiq/coredevice/ad53xx.py index 3445555d9..9a2b8eb2e 100644 --- a/artiq/coredevice/ad53xx.py +++ b/artiq/coredevice/ad53xx.py @@ -127,9 +127,9 @@ class AD53xx: transactions (default: 1) :param div_write: SPI clock divider for write operations (default: 4, 50MHz max SPI clock with {t_high, t_low} >=8ns) - :param div_read: SPI clock divider for read operations (default: 8, not - optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO - valid) + :param div_read: SPI clock divider for read operations (default: 16, not + optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO + valid, and suggests the SPI speed for reads should be <=20 MHz) :param vref: DAC reference voltage (default: 5.) :param offset_dacs: Initial register value for the two offset DACs, device dependent and must be set correctly for correct voltage to mu diff --git a/artiq/coredevice/zotino.py b/artiq/coredevice/zotino.py index e56842be5..9052f589a 100644 --- a/artiq/coredevice/zotino.py +++ b/artiq/coredevice/zotino.py @@ -27,15 +27,15 @@ class Zotino(AD53xx): :param clr_device: CLR RTIO TTLOut channel name. :param div_write: SPI clock divider for write operations (default: 4, 50MHz max SPI clock) - :param div_read: SPI clock divider for read operations (default: 8, not - optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO - valid) + :param div_read: SPI clock divider for read operations (default: 16, not + optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO + valid, and suggests the SPI speed for reads should be <=20 MHz) :param vref: DAC reference voltage (default: 5.) :param core_device: Core device name (default: "core") """ def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None, - div_write=4, div_read=8, vref=5., core="core"): + div_write=4, div_read=16, vref=5., core="core"): AD53xx.__init__(self, dmgr=dmgr, spi_device=spi_device, ldac_device=ldac_device, clr_device=clr_device, chip_select=_SPI_CS_DAC, div_write=div_write,