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phaser: fix startup_kernel/ceil

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This commit is contained in:
Robert Jördens 2016-10-07 12:57:38 +02:00
parent 09434ec054
commit c846e758f1
1 changed files with 1 additions and 3 deletions
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4
artiq/examples/phaser/startup_kernel.py
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@ -1,5 +1,3 @@
from math import ceil
from artiq.experiment import * from artiq.experiment import *
from artiq.coredevice.ad9516_reg import * from artiq.coredevice.ad9516_reg import *
@ -52,7 +50,7 @@ class StartupKernel(EnvExperiment):
# FPGA deviceclk, dclk/4 # FPGA deviceclk, dclk/4
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2) self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
self.ad9154.clock_write(AD9516_DIVIDER_0_0, self.ad9154.clock_write(AD9516_DIVIDER_0_0,
(ceil(4/2)-1)*AD9516_DIVIDER_0_HIGH_CYCLES | (4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES) (4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF) self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)
self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT | self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |