From c846e758f154c450d051100c8c10621c55131be4 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Fri, 7 Oct 2016 12:57:38 +0200 Subject: [PATCH] phaser: fix startup_kernel/ceil --- artiq/examples/phaser/startup_kernel.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/artiq/examples/phaser/startup_kernel.py b/artiq/examples/phaser/startup_kernel.py index ecc31cd2a..db0c7bdb1 100644 --- a/artiq/examples/phaser/startup_kernel.py +++ b/artiq/examples/phaser/startup_kernel.py @@ -1,5 +1,3 @@ -from math import ceil - from artiq.experiment import * from artiq.coredevice.ad9516_reg import * @@ -52,7 +50,7 @@ class StartupKernel(EnvExperiment): # FPGA deviceclk, dclk/4 self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2) self.ad9154.clock_write(AD9516_DIVIDER_0_0, - (ceil(4/2)-1)*AD9516_DIVIDER_0_HIGH_CYCLES | + (4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES | (4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES) self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF) self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |