From c66efc0279bd4cc9b5ccd89d330d4b06e1111e14 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 20 Feb 2017 15:52:48 +0800 Subject: [PATCH] moninj: do not require a rsys clock domain --- artiq/gateware/rtio/moninj.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/rtio/moninj.py b/artiq/gateware/rtio/moninj.py index 4ca981c14..c730a4997 100644 --- a/artiq/gateware/rtio/moninj.py +++ b/artiq/gateware/rtio/moninj.py @@ -20,7 +20,7 @@ class Monitor(Module, AutoCSR): for cp in chan_probes: cp_sys = [] for p in cp: - vs = BusSynchronizer(len(p), "rio", "rsys") + vs = BusSynchronizer(len(p), "rio", "sys") self.submodules += vs self.comb += vs.i.eq(p) cp_sys.append(vs.o)