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rtio/dds: use write-only RT2WB 

This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
This commit is contained in:
Sebastien Bourdeauducq 2018-11-26 07:38:15 +08:00
parent 09141e5bee
commit c56c0ba41f
1 changed files with 1 additions and 1 deletions
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artiq/gateware/rtio/phy/dds.py
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@ -8,7 +8,7 @@ class AD9914(Module):
def __init__(self, pads, nchannels, onehot=False, **kwargs): def __init__(self, pads, nchannels, onehot=False, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio_phy")( self.submodules._ll = ClockDomainsRenamer("rio_phy")(
ad9_dds.AD9_DDS(pads, **kwargs)) ad9_dds.AD9_DDS(pads, **kwargs))
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus) self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus, write_only=True)
self.rtlink = self._rt2wb.rtlink self.rtlink = self._rt2wb.rtlink
self.probes = [Signal(32) for i in range(nchannels)] self.probes = [Signal(32) for i in range(nchannels)]