From c56c0ba41f4b3adfb38162191360d5153a110ef9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 26 Nov 2018 07:38:15 +0800 Subject: [PATCH] rtio/dds: use write-only RT2WB This saves one address bit and prevents issues with AD9914 and 8-bit addresses. --- artiq/gateware/rtio/phy/dds.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/rtio/phy/dds.py b/artiq/gateware/rtio/phy/dds.py index 7e5011bd4..c542937fa 100644 --- a/artiq/gateware/rtio/phy/dds.py +++ b/artiq/gateware/rtio/phy/dds.py @@ -8,7 +8,7 @@ class AD9914(Module): def __init__(self, pads, nchannels, onehot=False, **kwargs): self.submodules._ll = ClockDomainsRenamer("rio_phy")( ad9_dds.AD9_DDS(pads, **kwargs)) - self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus) + self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus, write_only=True) self.rtlink = self._rt2wb.rtlink self.probes = [Signal(32) for i in range(nchannels)]