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libfringe: bump

This commit is contained in:
occheung 2021-08-25 12:03:04 +08:00
parent 251cd4dcc6
commit c113cd6bf5
2 changed files with 5 additions and 5 deletions
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4
artiq/firmware/runtime/Cargo.toml
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@ -31,7 +31,7 @@ smoltcp = { version = "0.6.0", default-features = false, features = ["alloc", "e
riscv = { version = "0.6.0", features = ["inline-asm"] } riscv = { version = "0.6.0", features = ["inline-asm"] }
[dependencies.fringe] [dependencies.fringe]
git = "https://github.com/m-labs/libfringe" git = "https://git.m-labs.hk/M-Labs/libfringe.git"
rev = "b8a6d8f" rev = "9748bb"
default-features = false default-features = false
features = ["alloc"] features = ["alloc"]

6
artiq/firmware/runtime/sched.rs
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@ -50,7 +50,7 @@ enum WaitResult {
#[derive(Debug)] #[derive(Debug)]
struct Thread { struct Thread {
generator: Generator<WaitResult, WaitRequest, OwnedStack>, generator: Generator<'static, WaitResult, WaitRequest, OwnedStack>,
waiting_for: WaitRequest, waiting_for: WaitRequest,
interrupted: bool interrupted: bool
} }
@ -194,7 +194,7 @@ impl Scheduler {
#[derive(Clone)] #[derive(Clone)]
pub struct Io<'a> { pub struct Io<'a> {
yielder: Option<&'a Yielder<WaitResult, WaitRequest, OwnedStack>>, yielder: Option<&'a Yielder<WaitResult, WaitRequest>>,
spawned: Urc<RefCell<Vec<ThreadHandle>>>, spawned: Urc<RefCell<Vec<ThreadHandle>>>,
sockets: Urc<RefCell<SocketSet>>, sockets: Urc<RefCell<SocketSet>>,
} }
@ -207,7 +207,7 @@ impl<'a> Io<'a> {
handle handle
} }
fn yielder(&self) -> &'a Yielder<WaitResult, WaitRequest, OwnedStack> { fn yielder(&self) -> &'a Yielder<WaitResult, WaitRequest> {
self.yielder.expect("cannot suspend the scheduler thread") self.yielder.expect("cannot suspend the scheduler thread")
} }