mirror of https://github.com/m-labs/artiq.git
targets/pipstrello: fix mem_map
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@ -55,7 +55,7 @@ class _Peripherals(BaseSoC):
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
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