M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

doc: core device page

This commit is contained in:
Sebastien Bourdeauducq 2015-08-08 21:24:13 +08:00
parent 1818e8173b
commit c0030406c3
3 changed files with 21 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
doc/manual/fpga_board_ports.rst → doc/manual/core_device.rst
View File

@ -1,5 +1,24 @@
Core device
===========
.. _core-device-flash-storage:
Flash storage
*************
The core device contains some flash space that can be used to store
some configuration data.
This storage area is used to store the core device MAC address, IP address and even the idle kernel.
The flash storage area is one sector (typically 64 kB) large and is organized as a list
of key-value records.
This flash storage space can be accessed by using the artiq_coretool :ref:`core-device-access-tool`.
FPGA board ports
================
****************
KC705
-----

14
doc/manual/core_device_flash_storage.rst
View File

@ -1,14 +0,0 @@
.. _core-device-flash-storage:
Core device flash storage
=========================
The core device contains some flash space that can be used to store
some configuration data.
This storage area is used to store the core device MAC address, IP address and even the idle kernel.
The flash storage area is one sector (64 kB) large and is organized as a list
of key-value records.
This flash storage space can be accessed by using the artiq_coretool.py :ref:`core-device-access-tool`.

3
doc/manual/index.rst
View File

@ -11,12 +11,11 @@ Contents:
getting_started
developing_a_ndsp
management_system
core_device
core_language_reference
core_drivers_reference
protocols_reference
ndsp_reference
core_device_flash_storage
utilities
fpga_board_ports
default_network_ports
faq