diff --git a/doc/manual/fpga_board_ports.rst b/doc/manual/core_device.rst
similarity index 75%
rename from doc/manual/fpga_board_ports.rst
rename to doc/manual/core_device.rst
index 52bd8dffe..e4334db48 100644
--- a/doc/manual/fpga_board_ports.rst
+++ b/doc/manual/core_device.rst
@@ -1,5 +1,24 @@
+Core device
+===========
+
+.. _core-device-flash-storage:
+
+Flash storage
+*************
+
+The core device contains some flash space that can be used to store
+some configuration data.
+
+This storage area is used to store the core device MAC address, IP address and even the idle kernel.
+
+The flash storage area is one sector (typically 64 kB) large and is organized as a list
+of key-value records.
+
+This flash storage space can be accessed by using the artiq_coretool :ref:`core-device-access-tool`.
+
+
 FPGA board ports
-================
+****************
 
 KC705
 -----
diff --git a/doc/manual/core_device_flash_storage.rst b/doc/manual/core_device_flash_storage.rst
deleted file mode 100644
index cc5fe1b2d..000000000
--- a/doc/manual/core_device_flash_storage.rst
+++ /dev/null
@@ -1,14 +0,0 @@
-.. _core-device-flash-storage:
-
-Core device flash storage
-=========================
-
-The core device contains some flash space that can be used to store
-some configuration data.
-
-This storage area is used to store the core device MAC address, IP address and even the idle kernel.
-
-The flash storage area is one sector (64 kB) large and is organized as a list
-of key-value records.
-
-This flash storage space can be accessed by using the artiq_coretool.py :ref:`core-device-access-tool`.
diff --git a/doc/manual/index.rst b/doc/manual/index.rst
index 502ea2443..bcf584cf9 100644
--- a/doc/manual/index.rst
+++ b/doc/manual/index.rst
@@ -11,12 +11,11 @@ Contents:
     getting_started
     developing_a_ndsp
     management_system
+    core_device
     core_language_reference
     core_drivers_reference
     protocols_reference
     ndsp_reference
-    core_device_flash_storage
     utilities
-    fpga_board_ports
     default_network_ports
     faq