mirror of https://github.com/m-labs/artiq.git
suservo: use new rtio_output() API
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@ -1,4 +1,4 @@
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from artiq.language.core import kernel, delay, now_mu, delay_mu, portable
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from artiq.language.core import kernel, delay, delay_mu, portable
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from artiq.language.units import us, ns
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.coredevice import spi2 as spi
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@ -129,7 +129,7 @@ class SUServo:
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:param addr: Memory location address.
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:param value: Data to be written.
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"""
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rtio_output(now_mu(), self.channel, addr | WE, value)
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rtio_output((self.channel << 8) | addr | WE, value)
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delay_mu(self.ref_period_mu)
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@kernel
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@ -140,7 +140,7 @@ class SUServo:
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:param addr: Memory location address.
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"""
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rtio_output(now_mu(), self.channel, addr, 0)
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rtio_output((self.channel << 8) | addr, 0)
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return rtio_input_data(self.channel)
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@kernel
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@ -262,7 +262,7 @@ class Channel:
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:param en_iir: IIR updates enable
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:param profile: Active profile (0-31)
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"""
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rtio_output(now_mu(), self.channel, 0,
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rtio_output(self.channel << 8,
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en_out | (en_iir << 1) | (profile << 2))
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@kernel
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