M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
Code Issues Projects Releases Wiki Activity

drtio: fix master TSC KCSR readout

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2016-11-08 16:40:50 +08:00
parent 651d538217
commit bcb5053fb6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/drtio/rt_controller.py
View File

@ -38,7 +38,7 @@ class RTController(Module):
# master RTIO counter and counter synchronization
self.submodules.counter = RTIOCounter(64-fine_ts_width)
self.sync += If(self.kcsrs.counter_update.re,
self.kcsrs.counter.status.eq(self.counter.value_sys))
self.kcsrs.counter.status.eq(self.counter.value_sys << fine_ts_width))
tsc_correction = Signal(64)
self.csrs.tsc_correction.storage.attr.add("no_retiming")
self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)