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artiq
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Merge branch 'master' into drtio

This commit is contained in:
Sebastien Bourdeauducq 2016-11-08 16:11:18 +08:00
parent 8c86920364 6e77f65d50
commit 651d538217
1 changed files with 6 additions and 4 deletions
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10
artiq/compiler/transforms/llvm_ir_generator.py
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@ -1265,10 +1265,12 @@ class LLVMIRGenerator:
return ll.Undefined
# T result = {
# void *ptr = NULL;
# loop: int size = rpc_recv("tag", ptr);
# void *ret_ptr = alloca(sizeof(T));
# void *ptr = ret_ptr;
# loop: int size = recv_rpc(ptr);
# // Non-zero: Provide `size` bytes of extra storage for variable-length data.
# if(size) { ptr = alloca(size); goto loop; }
# else *(T*)ptr
# else *(T*)ret_ptr
# }
llprehead = self.llbuilder.basic_block
llhead = self.llbuilder.append_basic_block(name="rpc.head")
@ -1283,7 +1285,7 @@ class LLVMIRGenerator:
self.llbuilder.branch(llhead)
self.llbuilder.position_at_end(llhead)
llphi = self.llbuilder.phi(llslotgen.type, name="rpc.size")
llphi = self.llbuilder.phi(llslotgen.type, name="rpc.ptr")
llphi.add_incoming(llslotgen, llprehead)
if llunwindblock:
llsize = self.llbuilder.invoke(self.llbuiltin("recv_rpc"), [llphi],