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gateware: add moninj to drtio targets

This commit is contained in:
Sebastien Bourdeauducq 2017-02-21 21:54:47 +08:00
parent a12876b239
commit b455ea447d
2 changed files with 8 additions and 0 deletions
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5
artiq/gateware/targets/kc705_drtio_master.py
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@ -99,6 +99,11 @@ class Master(MiniSoC, AMPSoC):
phy = ttl_simple.Inout(platform.request(sma)) phy = ttl_simple.Inout(platform.request(sma))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels, 3) self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
self.csr_devices.append("rtio_core") self.csr_devices.append("rtio_core")

3
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -44,6 +44,9 @@ class Satellite(BaseSoC):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.comb += platform.request("sfp_tx_disable_n").eq(1) self.comb += platform.request("sfp_tx_disable_n").eq(1)
if cfg == "simple_gbe": if cfg == "simple_gbe":
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock