From b455ea447dda334735adef086664bfcd3f072e2b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 21 Feb 2017 21:54:47 +0800 Subject: [PATCH] gateware: add moninj to drtio targets --- artiq/gateware/targets/kc705_drtio_master.py | 5 +++++ artiq/gateware/targets/kc705_drtio_satellite.py | 3 +++ 2 files changed, 8 insertions(+) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index f1636fa16..0ffe8f241 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -99,6 +99,11 @@ class Master(MiniSoC, AMPSoC): phy = ttl_simple.Inout(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) + + self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") + self.submodules.rtio_core = rtio.Core(rtio_channels, 3) self.csr_devices.append("rtio_core") diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py index 5a74f023d..b7c26f68f 100755 --- a/artiq/gateware/targets/kc705_drtio_satellite.py +++ b/artiq/gateware/targets/kc705_drtio_satellite.py @@ -44,6 +44,9 @@ class Satellite(BaseSoC): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") + self.comb += platform.request("sfp_tx_disable_n").eq(1) if cfg == "simple_gbe": # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock