gateware: clean up and integrate QC2 modifications from Daniel

artiq/gateware/nist_qc2.py

@@ -18,6 +18,19 @@ fmc_adapter_io = [
     ("ttl", 13, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
     ("ttl", 14, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
     ("ttl", 15, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
+    ("ttl", 16, Pins("LPC:LA13_N"), IOStandard("LVTTL")),
+    ("ttl", 17, Pins("LPC:LA14_N"), IOStandard("LVTTL")),
+    ("ttl", 18, Pins("LPC:LA17_CC_P"), IOStandard("LVTTL")),
+    ("ttl", 19, Pins("LPC:LA17_CC_N"), IOStandard("LVTTL")),
+    ("ttl", 20, Pins("LPC:LA18_CC_P"), IOStandard("LVTTL")),
+    ("ttl", 21, Pins("LPC:LA18_CC_N"), IOStandard("LVTTL")),
+    ("ttl", 22, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
+    ("ttl", 23, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
+    ("ttl", 24, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
+    ("ttl", 25, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
+    ("ttl", 26, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
+    ("ttl", 27, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
+
 
     ("dds", 0,
         Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N "
@@ -28,7 +41,7 @@ fmc_adapter_io = [
                             "LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
         Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
                                 "LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
-                                "LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
+                                "LPC:LA30_N LPC:LA33_P LPC:LA33_N LPC:LA32_P")),
         Subsignal("fud", Pins("LPC:LA21_N")),
         Subsignal("wr_n", Pins("LPC:LA24_P")),
         Subsignal("rd_n", Pins("LPC:LA25_N")),
@@ -36,7 +49,7 @@ fmc_adapter_io = [
         IOStandard("LVTTL")),
 
     ("i2c", 0,
-        Subsignal("scl", Pins("LPC:IIC_SLC")),
+        Subsignal("scl", Pins("LPC:IIC_SCL")),
         Subsignal("sda", Pins("LPC:IIC_SDA")),
         IOStandard("LVCMOS25")),
 
@@ -50,29 +63,4 @@ fmc_adapter_io = [
         Subsignal("n", Pins("LPC:CLK1_M2C_N")),
         IOStandard("LVDS")),
 
-    ("la32", 0,
-        Subsignal("p", Pins("LPC:LA32_P")),
-        Subsignal("n", Pins("LPC:LA32_N")),
-        IOStandard("LVDS")),
-
-    ("spi", 0,
-        Subsignal("clk", Pins("LPC:LA13_N")),
-        Subsignal("ce", Pins("LPC:LA14_N")),
-        Subsignal("mosi", Pins("LPC:LA17_CC_P")),
-        Subsignal("miso", Pins("LPC:LA17_CC_N")),
-        IOStandard("LVTTL")),
-
-    ("spi", 1,
-        Subsignal("clk", Pins("LPC:LA18_CC_P")),
-        Subsignal("ce", Pins("LPC:LA18_CC_N")),
-        Subsignal("mosi", Pins("LPC:LA23_P")),
-        Subsignal("miso", Pins("LPC:LA23_N")),
-        IOStandard("LVTTL")),
-
-    ("spi", 2,
-        Subsignal("clk", Pins("LPC:LA27_P")),
-        Subsignal("ce", Pins("LPC:LA26_P")),
-        Subsignal("mosi", Pins("LPC:LA27_N")),
-        Subsignal("miso", Pins("LPC:LA26_N")),
-        IOStandard("LVTTL")),
 ]

artiq/gateware/targets/kc705.py

@@ -213,6 +213,10 @@ class NIST_QC1(_NIST_QCx):
 
 
 class NIST_QC2(_NIST_QCx):
+    """
+    NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
+    and 12 DDS channels.  Current implementation for single backplane.  
+    """
     def __init__(self, cpu_type="or1k", **kwargs):
         _NIST_QCx.__init__(self, cpu_type, **kwargs)
 
@@ -220,18 +224,16 @@ class NIST_QC2(_NIST_QCx):
         platform.add_extension(nist_qc2.fmc_adapter_io)
 
         rtio_channels = []
-        for i in range(16):
+        # TTL0-23 are In+Out capable
-            if i == 14:
+        for i in range(24):
-                # TTL14 is for the clock generator
+            phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
-                continue
+            self.submodules += phy
-            if i % 4 == 3:
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
-                phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
+        # TTL24-26 are output only
-                self.submodules += phy
+        for i in range(24, 27):
-                rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+            phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
-            else:
+            self.submodules += phy
-                phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
+            rtio_channels.append(rtio.Channel.from_phy(phy))
-                self.submodules += phy
-                rtio_channels.append(rtio.Channel.from_phy(phy))
 
         phy = ttl_simple.Inout(platform.request("user_sma_gpio_n"))
         self.submodules += phy
@@ -241,15 +243,16 @@ class NIST_QC2(_NIST_QCx):
         rtio_channels.append(rtio.Channel.from_phy(phy))
         self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
 
-        phy = ttl_simple.ClockGen(platform.request("ttl", 14))
+        # TTL27 is for the clock generator
+        phy = ttl_simple.ClockGen(platform.request("ttl", 27))
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
         self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
-        self.config["DDS_CHANNEL_COUNT"] = 11
+        self.config["DDS_CHANNEL_COUNT"] = 12
         self.config["DDS_AD9914"] = True
         self.config["DDS_ONEHOT_SEL"] = True
-        phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
+        phy = dds.AD9914(platform.request("dds"), 12, onehot=True)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy,
                                                    ofifo_depth=512,