From b29e2d5bfe19fd8187175fc9c65b0e00795d1948 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 24 Jan 2017 22:25:58 +0000
Subject: [PATCH] Globally update UART baudrate to 921600.

---
 artiq/firmware/runtime/lib.rs                   | 1 -
 artiq/frontend/artiq_devtool.py                 | 2 +-
 artiq/gateware/targets/kc705_dds.py             | 1 +
 artiq/gateware/targets/kc705_drtio_master.py    | 1 +
 artiq/gateware/targets/kc705_drtio_satellite.py | 1 +
 artiq/gateware/targets/phaser.py                | 1 +
 artiq/gateware/targets/pipistrello.py           | 1 +
 doc/manual/installing_from_source.rst           | 4 ++--
 8 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/artiq/firmware/runtime/lib.rs b/artiq/firmware/runtime/lib.rs
index ec3fa90a6..4354460e4 100644
--- a/artiq/firmware/runtime/lib.rs
+++ b/artiq/firmware/runtime/lib.rs
@@ -57,7 +57,6 @@ mod moninj;
 mod analyzer;
 
 fn startup() {
-    board::uart::set_speed(921600);
     board::clock::init();
     info!("ARTIQ runtime starting...");
     info!("software version {}", cfg!(git_describe));
diff --git a/artiq/frontend/artiq_devtool.py b/artiq/frontend/artiq_devtool.py
index e6ad49129..a4204d0c3 100644
--- a/artiq/frontend/artiq_devtool.py
+++ b/artiq/frontend/artiq_devtool.py
@@ -100,7 +100,7 @@ def main():
 
             logger.info("Booting runtime")
             flterm = run_command(
-                "{env} python3 flterm.py {serial} " +
+                "{env} python3 flterm.py {serial} --speed 921600" +
                 "--kernel /tmp/{tmp}/runtime.bin " +
                 ("--upload-only" if action == "boot" else "--output-only"))
             artiq_flash = run_command(
diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py
index dd6cafc6f..5c3ff5072 100755
--- a/artiq/gateware/targets/kc705_dds.py
+++ b/artiq/gateware/targets/kc705_dds.py
@@ -112,6 +112,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
+                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
         if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
index f1b2f275b..3f10857f7 100755
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@@ -33,6 +33,7 @@ class Master(MiniSoC, AMPSoC):
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
+                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
 
diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py
index 151092586..af11ea703 100755
--- a/artiq/gateware/targets/kc705_drtio_satellite.py
+++ b/artiq/gateware/targets/kc705_drtio_satellite.py
@@ -131,6 +131,7 @@ class Satellite(BaseSoC):
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
                  ident=artiq_version,
+                 uart_baudrate=921600,
                  **kwargs)
 
         platform = self.platform
diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py
index e13efc579..4df5aa6d3 100755
--- a/artiq/gateware/targets/phaser.py
+++ b/artiq/gateware/targets/phaser.py
@@ -169,6 +169,7 @@ class Phaser(MiniSoC, AMPSoC):
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
+                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
         self.platform.toolchain.bitstream_commands.extend([
diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
index f7fc45a71..d81d6d2e4 100755
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@@ -160,6 +160,7 @@ class Demo(BaseSoC, AMPSoC):
                          l2_size=64*1024,
                          ident=artiq_version,
                          clk_freq=75*1000*1000,
+                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
 
diff --git a/doc/manual/installing_from_source.rst b/doc/manual/installing_from_source.rst
index 9db43a53b..49e72987a 100644
--- a/doc/manual/installing_from_source.rst
+++ b/doc/manual/installing_from_source.rst
@@ -187,7 +187,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
 * Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
 
-        $ flterm /dev/ttyUSB1
+        $ flterm /dev/ttyUSB1 --speed 921600
         MiSoC BIOS   http://m-labs.hk
         [...]
         Booting from flash...
@@ -197,7 +197,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
 .. note:: flterm is part of MiSoC. If you installed MiSoC with ``setup.py develop --user``, the flterm launcher is in ``~/.local/bin``.
 
-The communication parameters are 115200 8-N-1. Ensure that your user has access
+The communication parameters are 921600 8-N-1. Ensure that your user has access
 to the serial device (``sudo adduser $USER dialout`` assuming standard setup).
 
 .. _installing-the-host-side-software: