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artiq
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kernel: flush cache before mod_init 

This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
This commit is contained in:
occheung 2021-09-10 11:07:51 +08:00
parent d50e24acb1
commit b091d8cb66
1 changed files with 3 additions and 0 deletions
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artiq/firmware/ksupport/lib.rs
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@ -498,6 +498,9 @@ pub unsafe fn main() {
ptr::write_bytes(__bss_start as *mut u8, 0, (_end - __bss_start) as usize); ptr::write_bytes(__bss_start as *mut u8, 0, (_end - __bss_start) as usize);
board_misoc::cache::flush_cpu_dcache();
board_misoc::cache::flush_cpu_icache();
(mem::transmute::<u32, fn()>(__modinit__))(); (mem::transmute::<u32, fn()>(__modinit__))();
if let Some(typeinfo) = typeinfo { if let Some(typeinfo) = typeinfo {