M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

drop SI5324_SAYMA_REF

This commit is contained in:
Sebastien Bourdeauducq 2019-06-14 14:03:48 +08:00
parent 995a4428e7
commit b04e15741b
2 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/firmware/runtime/main.rs
View File

@ -138,7 +138,7 @@ fn startup() {
fn setup_si5324_as_synthesizer() fn setup_si5324_as_synthesizer()
{ {
// 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth // 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth
#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))] #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings { = board_artiq::si5324::FrequencySettings {
n1_hs : 10, n1_hs : 10,
@ -151,7 +151,7 @@ fn setup_si5324_as_synthesizer()
crystal_ref: false crystal_ref: false
}; };
// 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth // 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth
#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))] #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings { = board_artiq::si5324::FrequencySettings {
n1_hs : 5, n1_hs : 5,
@ -164,7 +164,7 @@ fn setup_si5324_as_synthesizer()
crystal_ref: false crystal_ref: false
}; };
// 125MHz output, from crystal, 7 Hz // 125MHz output, from crystal, 7 Hz
#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", not(si5324_ext_ref)))] #[cfg(all(rtio_frequency = "125.0", not(si5324_ext_ref)))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings { = board_artiq::si5324::FrequencySettings {
n1_hs : 10, n1_hs : 10,
@ -177,7 +177,7 @@ fn setup_si5324_as_synthesizer()
crystal_ref: true crystal_ref: true
}; };
// 150MHz output, from crystal // 150MHz output, from crystal
#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "150.0", not(si5324_ext_ref)))] #[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref)))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings { = board_artiq::si5324::FrequencySettings {
n1_hs : 9, n1_hs : 9,
@ -190,7 +190,7 @@ fn setup_si5324_as_synthesizer()
crystal_ref: true crystal_ref: true
}; };
// 100MHz output, from crystal. Also used as reference for Sayma HMC830. // 100MHz output, from crystal. Also used as reference for Sayma HMC830.
#[cfg(any(si5324_sayma_ref, all(rtio_frequency = "100.0", not(si5324_ext_ref))))] #[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref)))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings { = board_artiq::si5324::FrequencySettings {
n1_hs : 9, n1_hs : 9,

1
artiq/gateware/targets/sayma_amc.py
View File

@ -151,7 +151,6 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
self.config["I2C_BUS_COUNT"] = 1 self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
# ensure pins are properly biased and terminated # ensure pins are properly biased and terminated
si5324_clkout = platform.request("cdr_clk_clean", 0) si5324_clkout = platform.request("cdr_clk_clean", 0)