phaser: add hitl test exercising the complete API

This commit is contained in:
Robert Jördens 2020-09-22 15:35:19 +00:00
parent 85d16e3e5f
commit ad096f294c
1 changed files with 34 additions and 0 deletions

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import unittest
from artiq.experiment import *
from artiq.test.hardware_testbench import ExperimentCase
from artiq.language.core import kernel, delay
from artiq.language.units import us
class PhaserExperiment(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("phaser0")
@kernel
def run(self):
self.core.reset()
# The Phaser initialization performs a comprehensive test:
# * Fastlink bringup
# * Fastlink error counter
# * Board identification
# * Hardware identification
# * SPI write, readback, timing
# * Temperature readout
# * DAC identification, IOTEST, alarm sweep, PLL configuration, FIFO
# alignmend
# * DUC+Oscillator configuration, data end-to-end verification and
# readback
# * Attenuator write and readback
# * TRF bringup PLL locking
self.phaser0.init()
class PhaserTest(ExperimentCase):
def test(self):
self.execute(PhaserExperiment)