mirror of https://github.com/m-labs/artiq.git
libboard/sdram: add gap for write leveling
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@ -132,6 +132,12 @@ mod ddr {
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if !incr_delay() { break }
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if !incr_delay() { break }
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dq = ptr::read_volatile(dq_addr);
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dq = ptr::read_volatile(dq_addr);
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}
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}
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// Get a bit further into the 0 zone
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#[cfg(kusddrphy)]
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for _ in 0..32 {
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incr_delay();
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}
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}
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}
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while dq == 0 {
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while dq == 0 {
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