diff --git a/artiq/gateware/rtio/phy/ttl_serdes_7series.py b/artiq/gateware/rtio/phy/ttl_serdes_7series.py
index 018762984..846cc6fc3 100644
--- a/artiq/gateware/rtio/phy/ttl_serdes_7series.py
+++ b/artiq/gateware/rtio/phy/ttl_serdes_7series.py
@@ -31,6 +31,32 @@ class _OSERDESE2_8X(Module):
                                       o_O=pad, o_OB=pad_n)
 
 
+class _ISERDESE2_8X(Module):
+    def __init__(self, pad, pad_n=None):
+        self.o = Signal(8)
+        self.i = Signal(8)
+        self.oe = Signal()
+
+        # # #
+
+        pad_i = Signal()
+        i = self.i
+        self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
+                                  p_DATA_WIDTH=8,
+                                  p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
+                                  o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
+                                  o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
+                                  i_D=pad_i,
+                                  i_CLK=ClockSignal("rtiox4"),
+                                  i_CLKB=~ClockSignal("rtiox4"),
+                                  i_CE1=1, i_RST=0,
+                                  i_CLKDIV=ClockSignal("rio_phy"))
+        if pad_n is None:
+            self.comb += pad_i.eq(pad)
+        else:
+            self.specials += Instance("IBUFDS", o_O=pad_i, i_I=pad, i_IB=pad_n)
+
+
 class _IOSERDESE2_8X(Module):
     def __init__(self, pad, pad_n=None):
         self.o = Signal(8)
@@ -80,3 +106,9 @@ class Inout_8X(ttl_serdes_generic.Inout):
         serdes = _IOSERDESE2_8X(pad, pad_n)
         self.submodules += serdes
         ttl_serdes_generic.Inout.__init__(self, serdes)
+
+class Input_8X(ttl_serdes_generic.Inout):
+    def __init__(self, pad, pad_n=None):
+        serdes = _ISERDESE2_8X(pad, pad_n)
+        self.submodules += serdes
+        ttl_serdes_generic.Inout.__init__(self, serdes)