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sayma: clean up serwb comments

This commit is contained in:
Sebastien Bourdeauducq 2017-08-31 11:42:01 +08:00
parent 660f9856ec
commit a67659338d
2 changed files with 1 additions and 10 deletions
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4
artiq/gateware/targets/sayma_amc_standalone.py
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@ -57,9 +57,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
] ]
# AMC/RTM serwb # AMC/RTM serwb
# TODO: cleanup (same comments as in sayma_rtm.py)
# serwb SERDES
serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1) serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1)
self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk) self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
self.submodules += serwb_pll self.submodules += serwb_pll
@ -80,7 +77,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
serwb_phy.serdes.cd_serwb_serdes.clk, serwb_phy.serdes.cd_serwb_serdes.clk,
serwb_phy.serdes.cd_serwb_serdes_5x.clk) serwb_phy.serdes.cd_serwb_serdes_5x.clk)
# serwb slave
serwb_core = serwb.core.SERWBCore(serwb_phy, int(self.clk_freq), mode="slave") serwb_core = serwb.core.SERWBCore(serwb_phy, int(self.clk_freq), mode="slave")
self.submodules += serwb_core self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus) self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)

7
artiq/gateware/targets/sayma_rtm.py
View File

@ -69,7 +69,6 @@ CSR_RANGE_SIZE = 0x800
class SaymaRTM(Module): class SaymaRTM(Module):
def __init__(self, platform): def __init__(self, platform):
csr_devices = [] csr_devices = []
@ -98,10 +97,7 @@ class SaymaRTM(Module):
csr_devices.append("converter_spi") csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0) self.comb += platform.request("hmc7043_reset").eq(0)
# TODO: avoid having a "serdes" clock domain at the top level, rename to "serwb_serdes" or similar. # AMC/RTM serwb
# TODO: the above also applies to sayma_amc_standalone.py.
# serwb SERDES
serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1) serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1)
self.submodules += serwb_pll self.submodules += serwb_pll
@ -121,7 +117,6 @@ class SaymaRTM(Module):
serwb_phy.serdes.cd_serwb_serdes.clk, serwb_phy.serdes.cd_serwb_serdes.clk,
serwb_phy.serdes.cd_serwb_serdes_5x.clk) serwb_phy.serdes.cd_serwb_serdes_5x.clk)
# serwb master
serwb_core = serwb.core.SERWBCore(serwb_phy, int(clk_freq), mode="master") serwb_core = serwb.core.SERWBCore(serwb_phy, int(clk_freq), mode="master")
self.submodules += serwb_core self.submodules += serwb_core