From a67659338d7e59764e9e45b993abea31571f5d9e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 31 Aug 2017 11:42:01 +0800 Subject: [PATCH] sayma: clean up serwb comments --- artiq/gateware/targets/sayma_amc_standalone.py | 4 ---- artiq/gateware/targets/sayma_rtm.py | 7 +------ 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py index 8ef5cf1b8..69a3bc437 100755 --- a/artiq/gateware/targets/sayma_amc_standalone.py +++ b/artiq/gateware/targets/sayma_amc_standalone.py @@ -57,9 +57,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC): ] # AMC/RTM serwb - # TODO: cleanup (same comments as in sayma_rtm.py) - - # serwb SERDES serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1) self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk) self.submodules += serwb_pll @@ -80,7 +77,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC): serwb_phy.serdes.cd_serwb_serdes.clk, serwb_phy.serdes.cd_serwb_serdes_5x.clk) - # serwb slave serwb_core = serwb.core.SERWBCore(serwb_phy, int(self.clk_freq), mode="slave") self.submodules += serwb_core self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 797228e4e..d7906d9d7 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -69,7 +69,6 @@ CSR_RANGE_SIZE = 0x800 class SaymaRTM(Module): - def __init__(self, platform): csr_devices = [] @@ -98,10 +97,7 @@ class SaymaRTM(Module): csr_devices.append("converter_spi") self.comb += platform.request("hmc7043_reset").eq(0) - # TODO: avoid having a "serdes" clock domain at the top level, rename to "serwb_serdes" or similar. - # TODO: the above also applies to sayma_amc_standalone.py. - - # serwb SERDES + # AMC/RTM serwb serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1) self.submodules += serwb_pll @@ -121,7 +117,6 @@ class SaymaRTM(Module): serwb_phy.serdes.cd_serwb_serdes.clk, serwb_phy.serdes.cd_serwb_serdes_5x.clk) - # serwb master serwb_core = serwb.core.SERWBCore(serwb_phy, int(clk_freq), mode="master") self.submodules += serwb_core