M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00
Code Issues Projects Releases Wiki Activity

style

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2016-03-29 16:19:03 +08:00
parent 1a513634ff
commit a545598d4c
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/coredevice/core.py
View File

@ -60,8 +60,8 @@ class Core:
"""
kernel_constant_attributes = {
'core', 'ref_period', 'coarse_ref_period', 'ref_multiplier',
'external_clock',
"core", "ref_period", "coarse_ref_period", "ref_multiplier",
"external_clock",
}
def __init__(self, dmgr, ref_period, external_clock=False,

6
artiq/coredevice/dds.py
View File

@ -29,7 +29,7 @@ def dds_batch_exit() -> TNone:
class _BatchContextManager:
kernel_constant_attributes = {'core', 'core_dds'}
kernel_constant_attributes = {"core", "core_dds"}
def __init__(self, core_dds):
self.core_dds = core_dds
@ -53,7 +53,7 @@ class CoreDDS:
phase-locked multiple of the RTIO clock.
"""
kernel_constant_attributes = {'core', 'sysclk', 'batch'}
kernel_constant_attributes = {"core", "sysclk", "batch"}
def __init__(self, dmgr, sysclk, core_device="core"):
self.core = dmgr.get(core_device)
@ -89,7 +89,7 @@ class _DDSGeneric:
"""
kernel_constant_attributes = {
'core', 'core_dds', 'bus_channel', 'channel', 'pow_width'
"core", "core_dds", "bus_channel", "channel", "pow_width"
}
def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"):