From a545598d4c2ff84e14fc15c781c3904e28c4bf92 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 29 Mar 2016 16:19:03 +0800
Subject: [PATCH] style

---
 artiq/coredevice/core.py | 4 ++--
 artiq/coredevice/dds.py  | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py
index 1b3e10fdb..f500cfa6b 100644
--- a/artiq/coredevice/core.py
+++ b/artiq/coredevice/core.py
@@ -60,8 +60,8 @@ class Core:
     """
 
     kernel_constant_attributes = {
-        'core', 'ref_period', 'coarse_ref_period', 'ref_multiplier',
-        'external_clock',
+        "core", "ref_period", "coarse_ref_period", "ref_multiplier",
+        "external_clock",
     }
 
     def __init__(self, dmgr, ref_period, external_clock=False,
diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py
index 120ede4c1..7c81efcaa 100644
--- a/artiq/coredevice/dds.py
+++ b/artiq/coredevice/dds.py
@@ -29,7 +29,7 @@ def dds_batch_exit() -> TNone:
 
 
 class _BatchContextManager:
-    kernel_constant_attributes = {'core', 'core_dds'}
+    kernel_constant_attributes = {"core", "core_dds"}
 
     def __init__(self, core_dds):
         self.core_dds = core_dds
@@ -53,7 +53,7 @@ class CoreDDS:
         phase-locked multiple of the RTIO clock.
     """
 
-    kernel_constant_attributes = {'core', 'sysclk', 'batch'}
+    kernel_constant_attributes = {"core", "sysclk", "batch"}
 
     def __init__(self, dmgr, sysclk, core_device="core"):
         self.core = dmgr.get(core_device)
@@ -89,7 +89,7 @@ class _DDSGeneric:
     """
 
     kernel_constant_attributes = {
-        'core', 'core_dds', 'bus_channel', 'channel', 'pow_width'
+        "core", "core_dds", "bus_channel", "channel", "pow_width"
     }
 
     def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"):