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Revert "fir: different adder layout" 

This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866.
This commit is contained in:
Robert Jördens 2016-12-14 01:07:35 +01:00
parent 93076b8efa
commit a451b675c9
1 changed files with 4 additions and 5 deletions
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9
artiq/gateware/dsp/fir.py
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@ -102,19 +102,18 @@ class ParallelFIR(Module):
for j in range(p): for j in range(p):
# Make products # Make products
o = Signal((width + shift, True)) o = []
for i, c in enumerate(coefficients): for i, c in enumerate(coefficients):
# simplify for halfband and symmetric filters # simplify for halfband and symmetric filters
if c == 0 or c in coefficients[i + 1:]: if c == 0 or c in coefficients[i + 1:]:
continue continue
m = Signal.like(o) m = Signal((width + shift, True))
self.sync += m.eq(c*reduce(add, [ self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
])) ]))
o0, o = o, Signal.like(o) o.append(m)
self.comb += o.eq(o0 + m)
# Make sum # Make sum
self.sync += self.o[j].eq(o >> shift) self.sync += self.o[j].eq(reduce(add, o) >> shift)
def halfgen4_cascade(rate, width, order=None): def halfgen4_cascade(rate, width, order=None):