From a451b675c95d56b90e8c2238cdfa82792e0a54fa Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 14 Dec 2016 01:07:35 +0100 Subject: [PATCH] Revert "fir: different adder layout" This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866. --- artiq/gateware/dsp/fir.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/dsp/fir.py b/artiq/gateware/dsp/fir.py index 3c44d157f..6f1535528 100644 --- a/artiq/gateware/dsp/fir.py +++ b/artiq/gateware/dsp/fir.py @@ -102,19 +102,18 @@ class ParallelFIR(Module): for j in range(p): # Make products - o = Signal((width + shift, True)) + o = [] for i, c in enumerate(coefficients): # simplify for halfband and symmetric filters if c == 0 or c in coefficients[i + 1:]: continue - m = Signal.like(o) + m = Signal((width + shift, True)) self.sync += m.eq(c*reduce(add, [ xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c ])) - o0, o = o, Signal.like(o) - self.comb += o.eq(o0 + m) + o.append(m) # Make sum - self.sync += self.o[j].eq(o >> shift) + self.sync += self.o[j].eq(reduce(add, o) >> shift) def halfgen4_cascade(rate, width, order=None):