From a2ae5e470689dd12c133b9e8c20436e0d1b66fcb Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 3 Jun 2015 18:26:19 +0800 Subject: [PATCH] runtime: report TTL status over UDP --- artiq/gateware/rtio/__init__.py | 2 +- artiq/gateware/rtio/{monitor.py => moninj.py} | 1 + soc/runtime/Makefile | 2 +- soc/runtime/liblwip/lwipopts.h | 4 +- soc/runtime/main.c | 2 + soc/runtime/moninj.c | 83 +++++++++++++++++++ soc/runtime/moninj.h | 6 ++ soc/targets/artiq_kc705.py | 1 + soc/targets/artiq_pipistrello.py | 1 + 9 files changed, 98 insertions(+), 4 deletions(-) rename artiq/gateware/rtio/{monitor.py => moninj.py} (99%) create mode 100644 soc/runtime/moninj.c create mode 100644 soc/runtime/moninj.h diff --git a/artiq/gateware/rtio/__init__.py b/artiq/gateware/rtio/__init__.py index 6e6cc3550..2ca9db8aa 100644 --- a/artiq/gateware/rtio/__init__.py +++ b/artiq/gateware/rtio/__init__.py @@ -1,2 +1,2 @@ from artiq.gateware.rtio.core import Channel, RTIO -from artiq.gateware.rtio.monitor import Monitor +from artiq.gateware.rtio.moninj import Monitor diff --git a/artiq/gateware/rtio/monitor.py b/artiq/gateware/rtio/moninj.py similarity index 99% rename from artiq/gateware/rtio/monitor.py rename to artiq/gateware/rtio/moninj.py index 7b1fd8358..03494c2a1 100644 --- a/artiq/gateware/rtio/monitor.py +++ b/artiq/gateware/rtio/moninj.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.bank.description import * from migen.genlib.cdc import BusSynchronizer + class Monitor(Module, AutoCSR): def __init__(self, channels): chan_probes = [c.probes for c in channels] diff --git a/soc/runtime/Makefile b/soc/runtime/Makefile index 3cf2708dc..241448f37 100644 --- a/soc/runtime/Makefile +++ b/soc/runtime/Makefile @@ -1,6 +1,6 @@ include $(MSCDIR)/software/common.mak -OBJECTS := isr.o flash_storage.o clock.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o main.o +OBJECTS := isr.o flash_storage.o clock.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o moninj.o main.o OBJECTS_KSUPPORT := ksupport.o exception_jmp.o exceptions.o mailbox.o bridge.o rtio.o ttl.o dds.o CFLAGS += -Ilwip/src/include -Iliblwip diff --git a/soc/runtime/liblwip/lwipopts.h b/soc/runtime/liblwip/lwipopts.h index 14c2c2677..eff5a4aae 100644 --- a/soc/runtime/liblwip/lwipopts.h +++ b/soc/runtime/liblwip/lwipopts.h @@ -66,7 +66,7 @@ a lot of data that needs to be copied, this should be set high. */ #define MEMP_NUM_PBUF 64 /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One per active UDP "connection". */ -#define MEMP_NUM_UDP_PCB 1 +#define MEMP_NUM_UDP_PCB 2 /* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. */ #define MEMP_NUM_TCP_PCB 8 @@ -159,7 +159,7 @@ a lot of data that needs to be copied, this should be set high. */ #define DHCP_DOES_ARP_CHECK 0 /* ---------- UDP options ---------- */ -#define LWIP_UDP 0 +#define LWIP_UDP 1 #define UDP_TTL 255 diff --git a/soc/runtime/main.c b/soc/runtime/main.c index 95889fd07..fec357a0f 100644 --- a/soc/runtime/main.c +++ b/soc/runtime/main.c @@ -28,6 +28,7 @@ #include "test_mode.h" #include "kserver.h" #include "session.h" +#include "moninj.h" static void common_init(void) { @@ -139,6 +140,7 @@ static void regular_main(void) puts("Accepting sessions on Ethernet."); network_init(); kserver_init(); + moninj_init(); session_end(); while(1) { diff --git a/soc/runtime/moninj.c b/soc/runtime/moninj.c new file mode 100644 index 000000000..c379f97b8 --- /dev/null +++ b/soc/runtime/moninj.c @@ -0,0 +1,83 @@ +#include + +#ifdef CSR_ETHMAC_BASE + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "log.h" +#include "moninj.h" + +enum { + MONINJ_REQ_MONITOR = 1 +}; + +static struct udp_pcb *listen_pcb; + +struct monitor_reply { + long long int ttl_levels; + long long int ttl_oes; +}; + +static void moninj_monitor(const ip_addr_t *addr, u16_t port) +{ + struct monitor_reply reply; + int i; + struct pbuf *reply_p; + + reply.ttl_levels = 0; + reply.ttl_oes = 0; + for(i=0;ipayload, &reply, sizeof(struct monitor_reply)); + udp_sendto(listen_pcb, reply_p, addr, port); + pbuf_free(reply_p); +} + +static void moninj_recv(void *arg, struct udp_pcb *upcb, struct pbuf *req, + const ip_addr_t *addr, u16_t port) +{ + if(req->len >= 1) { + switch(*(char *)req->payload) { + case MONINJ_REQ_MONITOR: + moninj_monitor(addr, port); + break; + default: + break; + } + } + pbuf_free(req); /* beware: addr may point into the req pbuf */ +} + +void moninj_init(void) +{ + listen_pcb = udp_new(); + if(!listen_pcb) { + log("Failed to create UDP listening PCB"); + return; + } + udp_bind(listen_pcb, IP_ADDR_ANY, 3250); + udp_recv(listen_pcb, moninj_recv, NULL); +} + +#endif /* CSR_ETHMAC_BASE */ diff --git a/soc/runtime/moninj.h b/soc/runtime/moninj.h new file mode 100644 index 000000000..1224b3b6e --- /dev/null +++ b/soc/runtime/moninj.h @@ -0,0 +1,6 @@ +#ifndef __MONINJ_H +#define __MONINJ_H + +void moninj_init(void); + +#endif /* __MONINJ_H */ diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index 5d0cefa68..439934cb9 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -76,6 +76,7 @@ class NIST_QC1(MiniSoC, AMPSoC): phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes)) + self.add_constant("RTIO_TTL_COUNT", len(rtio_channels)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.submodules.dds = RenameClockDomains( diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index 532ec0f85..e9be3d4b3 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -111,6 +111,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes)) + self.add_constant("RTIO_TTL_COUNT", len(rtio_channels)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.submodules.dds = RenameClockDomains(